Input buffers are used in many different systems to receive incoming signals and convert them to desired characteristics for a given system. For example, input buffers often receive signals at a voltage level of driver circuitry that transmitted the signals and convert the signals to a voltage of processing circuitry of a system component.
In devices used in certain systems such as optical systems, e.g., in framers, serializer/deserializers (SERDES) and other such devices, signaling between devices often occurs according to a low voltage differential signaling (LVDS) protocol. LVDS signals can be high speed signals typically provided at a low voltage, low power differential value. In general, LVDS signals are transmitted at a common mode voltage of 1.25 volts (V) with a swing between the differential voltages in the range of several hundred millivolts (mV). A voltage shift may occur between a level at which a driver transmits signals and a level at which a receiver receives such signals. Such a voltage difference may correspond to a common mode voltage difference, e.g., due to IR drops across a ground potential. Alternately, such voltage shifts may occur when an input buffer such as an LVDS input buffer is connected to an output buffer of another signaling protocol, such as a low voltage emitter coupled logic (ECL) or current mode logic driver, for example. Generally, the input common mode voltage (VICM) signals received by a receiver are in the range of approximately 0.5-2.35 V, in certain implementations.
As semiconductor devices advance, they are often powered at lower and lower supply voltages. For example, many of today's semiconductor devices are powered with a supply voltage of 1.3 V. Accordingly, when input common mode voltage signals are received at a higher level than the supply voltage, level shifting is first performed before any input buffer amplification or gain stages occur. As a result, this level shifting to a lower voltage causes a DC offset that is then manifested as noise when the signal is later amplified in further stages of an input buffer.
Typical input buffers used in LVDS signaling systems include transimpedance amplifiers (TIAs) that operate as level shifters. While such designs provide for a large common mode input range, a significant impedance mismatch may occur resulting in large offsets. Furthermore, the TIA needs a very large gain bandwidth to operate and also suffers from poor common mode rejection ratio (CMRR). CMRR is a ratio that indicates the amount of common mode rejection, i.e., the ability to reject noise that is coupled equally to the differential signals. Another solution for input buffers is to use a folded cascode amplifier. While this design improves upon the level shifter mismatches of a TIA design, input common mode voltage is limited on both the high and low sides. Also, a significant mismatch is present, and furthermore such an amplifier suffers from low bandwidth, which is unsuitable for high speed applications.
Accordingly, a need exists for an improved input buffer to handle incoming signals, especially where such signals may exceed a supply voltage of the input buffer.